A HFET (also known as a High Electron Mobility Transistor (HEMT)) is a field effect transistor incorporating a junction between two materials with different band gaps (i.e., a heterojunction) as the channel instead of a doped region as is generally the case for metal oxide silicon filed effect transistors (MOSFETs).
FIG. 1a depicts a conventional GaN HFET device structure with a buffer 10 of AlGaN disposed on a substrate 8. Buffers 10 of GaN are also known in the prior art. The channel layer 12 is a 40 nm thick layer of GaN and the barrier layer 14 is a 21 nm thick layer of uniform Al0.25Ga0.75N. While the layers shown in FIG. 1a are all Un-Intentionally Doped (UID) layers, it is known in the art to add some doping to some of these layers or to layers disposed between these layers. See, for example, Fujiwara “Technique for Development of High Current Density Heterojunction Field Effect Transistors based on (10-10)-Plane GaN By Delta-Doping” US Patent Publication 2011/0057198.
The structure of FIG. 1a is depicted before a gate structure is formed thereon. For higher frequency devices, the gate structure is typically a T-gate.
FIG. 3a depicts pulsed-IV measurements with Vgs=+1V and a 200 ns pulse-width of the conventional device of FIG. 1a. The current-collapse taken at Vds=2V is 35% for the conventional device of FIG. 1a. 
Current collapse has long been an issue for microwave and millimeter-wave AlGaN/GaN HFETs. Transistors can exhibit a phenomenon known as current collapse, where channel conductance is temporarily reduced after exposure to high voltage. This problem is typically mitigated by using SiN surface passivation. The gate is then fabricated by etching its foot through the SiN and then evaporating and lifting off the gate using a separate lithography step. This prior art process naturally creates a field-plate, and the resulting device is quite useful for frequencies up to the Ka band (26.5-40 GHz).
However, limitations on the gate length and parasitic capacitance introduced by the field plate preclude this process from being used for still higher frequencies. To reduce capacitances while having a short gate length, a “T-gate” structure is typically used. Unfortunately, T-gate devices typically have worse current collapse than field-plated devices because of inherent differences in the passivation process and changes to the E-field profile at the drain-edge of the gate of the device. This remains a major problem for high-frequency group III-nitride devices, particularly for GaN-based devices which can be used at frequencies above the Ka band.
Achieving good power performance at frequencies above the Ka band requires new approaches in the technology. First, T-gates should be used to achieve short gate length with low parasitic capacitance. However, it becomes more difficult to have good passivation of the surface traps with a T-gate process compared with a more conventional field-plated approach. The result is often a very high level of current collapse, which greatly limits output power and efficiency that is achievable in a power amplifier. This is a major limitation which prevents mainstream adoption of GaN HFETs in V-band and W-band applications.
The present invention reduces the level of current collapse compared to the techniques used in the prior art.